参数资料
型号: MC56F8036VLF
厂商: Freescale Semiconductor
文件页数: 79/164页
文件大小: 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
标准包装: 1,250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 32MHz
连通性: CAN,I²C,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 39
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 4K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 10x12b; D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
56F8036 Signal Pins
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
21
2.2 56F8036 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
VDD
31
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
VDD
38
VSS
19
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
30
VSS
39
VDDA
12
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSSA
13
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
VCAP
20
Supply
VCAP — Connect this pin to a 2.2μF or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See Section 10.2.1.
VCAP
37
RESET
(GPIOA7)
23
Input
Input/Open
Drain
Output
Input,
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
Return to Table 2-2
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