参数资料
型号: MC56F8356MFVE
厂商: Freescale Semiconductor
文件页数: 116/178页
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 144-LQFP
标准包装: 60
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 62
程序存储器容量: 264KB(132K x 16)
程序存储器类型: 闪存
RAM 容量: 10K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 16x12b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 144-LQFP
包装: 托盘
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8356 Technical Data, Rev. 13
42
Freescale Semiconductor
Preliminary
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory
map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have
an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no
effect.
The device’s external memory interface (EMI) can operate much like the 56F80x family’s EMI, or it can
be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1
are configured as PS and DS, in a mode compatible with earlier 56800 devices.
Eighteen address lines are required to shadow the first 192K of internal program space when booting
externally for development purposes. Therefore, the entire complement of on-chip memory cannot be
Data RAM
16KB
None
Program Boot Flash
16KB
Erase / Program via Flash Interface unit and word to CDBW
Table 4-2 OMR MB/MAL Value at Reset
OMR MB =
Flash Secured
State1, 2
1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
2. Changing MB in software will not affect Flash memory security.
OMR MA =
EXTBOOT Pin
Chip Operating Mode
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
0
1
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
1
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
1
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA
Chip Operating Mode
0
Use internal P-space memory map configuration
1
Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no
effect.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8356
56F8156
Use Restrictions
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