参数资料
型号: MC56F8356MFVE
厂商: Freescale Semiconductor
文件页数: 58/178页
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 144-LQFP
标准包装: 60
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 62
程序存储器容量: 264KB(132K x 16)
程序存储器类型: 闪存
RAM 容量: 10K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 16x12b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 144-LQFP
包装: 托盘
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8356 Technical Data, Rev. 13
150
Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
RD Deasserted to RD Asserted
tRDRD
-0.2342
0.00
RWSS,RWSH
MDAR3, 4
ns
WR Deasserted to WR Asserted
tWRWR
WWS=0
-1.279
0.75 + DCAEO
WWSS, WWSH
ns
WWS>0
-0.938
1.00
RD Deasserted to WR Asserted
tRDWR
WWS=0
-0.046
0.50
RWSH, WWSS,
MDAR3
ns
WWS>0
0.052
0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is acive in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration
tRA
16T
ns
RESET Deassertion to First External Address
Output3
tRDA
63T
64T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM
18T
ns
tIDM - FAST
14T
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
ns
tIG - FAST
14T
Delay from IRQA Assertion (exiting Wait) to
External Data Memory Access4
tIRI
22T
ns
tIRI -FAST
18T
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
tIF
22T
ns
tIF - FAST
18T
Table 10-16 External Memory Interface Timing (Continued)
Characteristic
Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
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