参数资料
型号: MC56F8356VFVE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封装: ROHS COMPLIANT, LQFP-144
文件页数: 121/178页
文件大小: 910K
代理商: MC56F8356VFVE
Data Map
56F8356 Technical Data, Rev. 13
Freescale Semiconductor
47
Preliminary
4.4 Data Map
Note: Data Flash is NOT available on the 56F8156 device.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus.
The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the
Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
2.
Table 4-6 Data Memory Map1
1. All addresses are 16-bit Word addresses, not byte addresses.
Begin/End
Address
EX = 02
2. In the Operating Mode Register (OMR).
EX = 1
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 3000
External Memory
X:$00 2FFF
X:$00 2000
On-Chip Data Flash
8KB
X:$00 1FFF
X:$00 0000
On-Chip Data RAM
16KB3
3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.
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