参数资料
型号: MC56F8356VFVE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封装: ROHS COMPLIANT, LQFP-144
文件页数: 94/178页
文件大小: 910K
代理商: MC56F8356VFVE
56F8356 Technical Data, Rev. 13
22
Freescale Semiconductor
Preliminary
GPIOB0
(A16)
33
Schmitt
Input/
Output
Input,
pull-up
enabled
Port B GPIO — This GPIO pin can be programmed as an input or
output pin.
Address Bus — A16 specifies one of the address lines for
external program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR), A16 and
EMI control signals are tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
After reset, the start-up state of GPIOB0 (GPIO or address) is
determined as a function of EXTBOOT, EMI_MODE and the Flash
security setting. See Table 4-4 for further information on when this
pin is configured as an address pin at reset. In all cases, this state
may be changed by writing to GPIOB_PER.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.
D0
(GPIOF9)
59
Input/
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D0 - D6 specify part of the data for external program or
data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), D0 - D6 are tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
Port F GPIO — These seven GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to the EMI Data Bus function.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF9, clear bit 9 in the GPIOF_PUR register.
D1
(GPIOF10)
60
D2
(GPIOF11)
72
D3
(GPIOF12)
75
D4
(GPIOF13)
76
D5
(GPIOF14)
77
D6
(GPIOF15)
78
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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