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参数资料
| 型号： | MC68302FC20CR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封装： | 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 |
| 文件页数： | 109/128页 |
| 文件大小： | 641K |
| 代理商： | MC68302FC20CR2 |
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Applications
6-2
MC68EN302 REFERENCE MANUAL
MOTOROLA
and the pin muxing that is used in the current MC68EN302 application.
Example: Write $5400 to MBC (MFC = 5, PPE = 1).
7. IER - The interrupt extension register replaces the MOD, ET7, ET6 and ET1 bits in the
302 GIMR.
The user MUST assure that the corresponding bits in the GIMR of the
internal 302 are all written as zeros for proper functionality of the MC68EN302. The
IER is reset to $0000 which configures the interrupt input pins as IPL2–IPL0 and sets
the module bus controller interrupt to level 5.
8. CSER0–CSER3. The MC68EN302 extends the functionality of that provided by the
internal 302 core chip selects through the programming of this register. Additional
functionality includes 8-bit bus operation as well as parity checking and generation.
9. PCSR - This register controls parity operation on the MC68EN302. Also, bits 9-8 show
the result of parity on the current DRAM bank.
10. DRAM controller initialization. Assume bank 0 is to be used, parity enabled, 0 wait
states.
DRAM Configuration Register (DCR) = $0501 (Enable refresh and parity in bank 0,
allow supervisor or user access)
DRAM Refresh Register (DRFRSH) = $0000 (Refresh every 4096 system clocks)
DRAM Base Address Registers
DBA0 = desired DRAM base address and size, bit 0 = 1
DBA1 = $0000 (reset value)
To ensure correct parity, write $0000 to each memory location used before running
other code.
11. Ethernet Controller Initialization. In this example the Ethernet Controller is initialized to
perform internal loopback of one frame. The received frame buffer will be 4 bytes
longer than the transmit buffer due to the CRC being appended by hardware.
ECNTRL = $0001 (Release RESET to the Ethernet Controller)
EDMA = $000B
WMRK = 01 (16 bytes)
BLIM = 011 (max DMA burst length of 8 bus transactions (16 bytes of data))
EMRBLR = $0600 (1536 bytes, this allows receiving a max size frame into a single
buffer).
IVEC = $0140
VG = 1 (bit 1–bit 0 of the interrupt vector will be modified).
INV7–INV0 = 40
INTR_MASK = $07BC (all interrupts enabled except BackOffDone, TransmitBuffer
and ReceiveBuffer).
ECNFIG = $0001 (enable internal loopback).
ETHER_TEST = $0000
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68302FC25 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Integrated Multiprotocol Processor User’s Manual |
| MC68302FC25C | 功能描述:IC MPU MULTI-PROTOCOL 132-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M683xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| MC68302FE16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Communications Controller |
| MC68302FE16C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Communications Controller |
| MC68302FE20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Communications Controller |
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