9- 2
MC68341 USER’S MANUAL
MOTOROLA
9.2 MEMORY MAP
The QSPM memory map is comprised of the global registers, the QSPI control and status
registers, and the QSPI RAM as shown in Figure 9-2. For an accurate location of the
QSPM in the MC68341 memory map, refer to Figure 4-1 SIM41 Module Register Block.
The QSPM memory map may be divided into two segments: supervisor-only data space
and assignable data space.
15
8 7
0
$800
QMCR
$802
QTEST
SUPERVISOR-ONLY DATA SPACE
$804
QILR
QIVR
$806
RESERVED
$808
$80A
$80C
$80E
$810
RESERVED
$812
RESERVED
$814
RESERVED
QPDR
$816
QPAR
QDDR
ASSIGNABLE DATA SPACE
$818
SPCR0
(SUPERVISOR-ONLY OR UNRESTRICTED)
$81A
SPCR1
$81C
SPCR2
$81E
SPCR3
SPSR
RESERVED
$900-1F
REC.RAM
$920-3F
TRAN.RAM
QUEUE RAM
$940-4F
COMD .RAM
$820-FF
RESERVED
Figure 9-2. QSPM Memory Map
The supervisor-only data space segment contains the QSPM global registers. These
registers define parameters needed by the QSPM to integrate with the CPU. Access to
these registers is permitted only when the CPU is operating in supervisor mode.
Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user accesses. The supervisor (SUPV) bit in the QSPM module
configuration register (QMCR) designates the assignable data space as either supervisor
or unrestricted. If SUPV is set, then the space is designated as supervisor-only space.
Access is then permitted only when the CPU is operating in supervisor mode. All attempts
to read supervisor data spaces when not in supervisor mode (CPU status register, S bit =
0) return a value of zero, and all attempts to write have no effect. If SUPV is clear, both
user and supervisor accesses are permitted. To clear SUPV in the QMCR, the CPU must
be in supervisor mode (CPU status register, S-bit = 1).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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