MOTOROLA
MC68341 USER’S MANUAL
9- 7
Table 9-3. Bit/Field Quick Reference Guide (Sheet 2 of 2)
Bit/Field
Mnemonic
Function
Register
Location
SUPV
Supervisor/Unrestricted
QMCR
QSPM
TQSM
Test QSPM Enable
QTEST
QSPM
TSBD
SPI Test Scan Path Select
QTEST
QSPM
WOMQ
Wired-OR Mode for QSPI Pins
SPCR0
QSPI
WREN
Wrap Enable
SPCR2
QSPI
WRTO
Wrap To Select
SPCR2
QSPI
9.4.1 Overall QSPM Configuration Summary
After reset, the QSPM remains in an idle state, requiring initialization of several registers
before any serial operations may begin execution. The following registers, fields, and bits
are fully described later in this section. A general sequence guide for initialization follows:
QMCR (refer to 9.4.2.1 QSPM Configuration Register (QMCR))
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This register must be initialized to properly configure:
—Interrupt arbitration identification number used by the entire QSPM module
—Supervisor/unrestricted bit (SUPV)
—FREEZE and/or STOP configuration should remain cleared to zero for normal
operation.
QIVR and QILR (refer to 9.4.2.3 QSPM Interrupt Level Register (QILR) and 9.4.2.4
QSPM Interrupt Vector Register (QIVR) )
These registers are written to choose the base vector number for the QSPM module and
interrupt level for the QSPI submodule.
QPDR and QDDR (refer 9.4.3.1 QSPM Port Data Register (QPDR) and 9.4.3.3
QSPM Data Direction Register (QDDR))
The pin control registers should be initialized in the order QPDR and then QDDR, thus
establishing the default state and direction of the QSPM pins.
For configuration of the QSPI submodule, initialize as follows:
RAM (refer to 9.5.4.6 QSPI RAM)
QPAR (refer 9.4.3.2 QSPM Pin Assignment Register (QPAR) )
Assignment of appropriate pins to the QSPI must be made with this register.
SPCR0 (refer 9.5.4.1 QSPI Control Register 0 (SPCR0))
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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