MOTOROLA
MC68341 USER’S MANUAL
9- 9
QMCR
$800
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9876543210
STOP
FRZ1
FRZ0
00000
SUPV
0
IARB
RESET:
0000000010000000
STOP—Stop Enable
1 = QSPM clock operation stopped
0 = Normal QSPM clock operation
STOP places the QSPM into a low power state by disabling the system clock in most
parts of the module. QMCR is the only register guaranteed to be readable while STOP
is asserted. The QSPI RAM is not readable; however, writes to RAM or any register are
guaranteed valid while STOP is asserted. STOP may be negated by the CPU and by
reset.
The system software must stop each submodule before asserting STOP to avoid
complications at restart and to avoid data corruption. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA
flag is set.
FRZ1—Freeze1
1 = Halt the QSPM (on a transfer boundary)
0 = Ignore the FREEZE signal on the IMB
FRZ1 determines what action is taken by the QSPM when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters the background mode.
NOTE
Ignoring the FREEZE signal can cause unpredictable results in
the background mode operation of the QSPM, because the
CPU is unable to service interrupt requests in this mode. If
FRZ1 equals one when the FREEZE line is asserted, the
QSPM comes to an orderly halt on a transfer boundary as if
HALT had been asserted. The output pins continue to drive
their last state. Once the FREEZE signal is negated, the
QSPM module restarts automatically.
FRZ0—Freeze0
Reserved for future enhancement.
Bits 12–8—Not Implemented
SUPV—Supervisor/Unrestricted
1 = Supervisor access
All registers in the QSPM are placed in supervisor-only space. For any access
from within user mode, address acknowledge (AACK) is not returned and the bus
cycle is transferred externally.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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