12-6
MC68341 USER’S MANUAL
MOTOROLA
12.6 CLOCK AC ELECTRICAL SPECIFICATIONS - PRELIMINARY
(GND = 0 Vdc, TA = 0 to 70
°C; see numbered notes)
CLOCK SPECIFICATIONS - Crystal Mode
3.3 V or 5.0 V
5.0 V
16.78 MHz
25.16 MHz
Num.
Characteristic
Symbol
Min
Max
Min
Max
Unit
System Frequency - Crystal Mode1
fsys
0.13
16.78
0.13
25.16
MHz
Crystal Frequency2
fXTAL
25
50
25
50
kHz
External Clock Input Frequency 3
fEXT
25
50
25
50
kHz
External Clock Duty Cycle
20
80
20
80
%
VCO Frequency Range
fVCO
0.1
51.2
0.1
51.2
MHz
PLL Start-up Time4
trc
—
20
—
20
ms
Limp Mode CLKOUT Frequency 5
SYNCR X-bit = 0 and Z-bit = 0
SYNCR X-bit = 1 and Z-bit = 0
flimp
—
8.39
16.78
—
8.39
16.78
MHz
CLKOUT stability 6
CLK
—
±1
—
±1
%
1
CLKOUT Period
tcyc
59.6
—
39.7
—
ns
CLKOUT Duty Cycle
47
53
47
53
%
2,3
CLKOUT Pulse Width
tCW
28
—
19
—
ns
4,5
CLKOUT Rise and Fall Times
tCrf
—
5
—
4
ns
NOTES:
1.
All crystal mode clock specifications are based on using a 32.768-kHz crystal for the input.
2.
The RTC requires a 32.768 kHz crystal or external clock for proper operation.
3.
EXTAL can be direct driven by an external oscillator source - refer to the DC Electrical Characteristics for
VIL/VIH requirements.
4.
Assumes that a stable VCCSYN is applied, that an external filter capacitor with a value of 0.1 F is attached to
the XFC pin, and that the crystal oscillator is stable. This specification also applies to the period required for PLL
lock after changing the W or Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is
running, and to the period required for the clock to lock after exiting LPSTOP.
5.
The X-bit in the SYNCR controls a divide-by-two scaler on the system clock output.
6.
CLKOUT stability is the average deviation from programmed frequency measured at maximum f sys.
Measurement is made with a stable external clock input applied using the PLL.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.