MOTOROLA
MC68341 USER’S MANUAL
2- 9
2.2.12 Interrupt Request Level
(IRQ7 — IRQ1)
These pins can be programmed to be either prioritized interrupt request lines or port B
parallel I/O.
IRQ7 – IRQ1
IRQ7, the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable
interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines.
Port B7 – B1
These pins can be used as port B parallel I/O. Refer to Section 4 System Integration
Module for more information on parallel I/O signals.
2.3 BUS CONTROL SIGNALS
These signals control the bus transfer operations of the MC68341. Refer to Section 3
Bus Operation for more information on these signals.
2.3.1 Data and Size Acknowledge (
DSACK1, DSACK0)
These two active-low input signals allow asynchronous data transfers and dynamic data
bus sizing between the MC68341 and external devices as listed in Table 2-12. During bus
cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the MC68341 to terminate the bus cycle and to latch the
data. During a write cycle, this indicates that the external device has successfully stored
the data and that the cycle may terminate.
Table 2-12.
DSACK Encoding
DSACK1
DSACK0
Result
1
Insert Wait States in Current Bus Cycle
1
0
Complete Cycle—Data Bus Port Size Is 8 Bits
0
1
Complete Cycle—Data Bus Port Size Is 16 Bits
0
Reserved—Defaults to 16-Bit Port Size. Can Be
Used for 32-Bit DMA Cycles
2.4 BUS ARBITRATION SIGNALS
The following signals are the bus arbitration control signals used to determine the bus
master. Refer to Section 3 Bus Operation for more information on these signals.
2.4.1 Bus Request (
BR)
This active-low input signal indicates that an external device needs to become the bus
master.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.