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参数资料
| 型号： | MC68HC05T7B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | SDIP-56 |
| 文件页数： | 106/109页 |
| 文件大小： | 9008K |
| 代理商： | MC68HC05T7B |
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Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
96
Computer Operating Properly Module (COP)
MOTOROLA
Computer Operating Properly Module (COP)
8.4 Operation
Operation of the COP module is discussed here.
8.4.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/VPP pin
voltage is between VSS and VDD. Periodically clearing the counter starts
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE:
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
8.4.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. (See timer status and control register
Note that the minimum COP timeout period is seven times the RTI
period. The COP is cleared asynchronously with the value in the RTI
divider; hence, the COP timeout period will vary between 7x and 8x the
RTI period.
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