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参数资料
| 型号： | MC68HC05T7B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | SDIP-56 |
| 文件页数： | 98/109页 |
| 文件大小： | 9008K |
| 代理商： | MC68HC05T7B |
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Technical Data
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
88
Parallel I/O Ports
MOTOROLA
Parallel I/O Ports
7.3.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. (See Section 9.
7.4 Port B
Port B is a 2-bit bidirectional port.
7.4.1 Port B Data Register
The port B data register contains a latch for each port B pin.
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each
port B pin is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
NOTE:
PB4–PB5 and PB0–PB1 should be configured as inputs at all times.
These bits are available for read/write but are not available externally.
Configuring them as inputs will ensure that the pulldown devices are
enabled, thus properly terminating them.
Address:
$0001
Bit 7
6
54321
Bit 0
Read:
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are
available for read/write but are not available externally. Configuring them as inputs will
ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
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