参数资料
型号: MC68HC705C9ACP
厂商: Freescale Semiconductor
文件页数: 5/118页
文件大小: 0K
描述: IC MCU 2.1MHZ 16K OTP 40-DIP
标准包装: 9
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 24
程序存储器容量: 16KB(16K x 8)
程序存储器类型: OTP
RAM 容量: 352 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
Electrical Specifications
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
102
Freescale Semiconductor
12.9 5.0-Vdc Serial Peripheral Interface Timing
No.
Characteristic(1)
1. V
DD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = –40 to +85°C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10.
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
f
OP
(M)
f
OP
(S)
dc
0.5
2.1
f
OP
MHz
1
Cycle time
Master
Slave
t
CYC
(M)
t
CYC
(S)
2.0
480
t
CYC
ns
2
Enable lead time
Master
Slave
t
LEAD
(M)
t
LEAD
(S)
(2)
240
ns
3
Enable lag time
Master
Slave
t
LAG
(M)
t
LAG
(S)
(2)
720
2. Signal production depends on software.
ns
4
Clock (SCK) high time
Master
Slave
t
W
(SCKH)M
t
W
(SCKH)S
340
190
ns
5
Clock (SCK) low time
Master
Slave
t
W
(SCKL)M
t
W
(SCKL)S
340
190
ns
6
Data setup time (inputs)
Master
Slave
t
SU
(M)
t
SU
(S)
100
ns
7
Data hold time (inputs)
Master
Slave
t
H
(M)
t
H
(S)
100
ns
8
Slave access time (time to data active from
high-impedance state)
t
A
0
120
ns
9
Slave disable time (hold time to high-impedance state)
t
DIS
240
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
3. Assumes 200 pF load on all SPI pins.
t
V
(M)
t
V
(S)
0.25
240
t
CYC
(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
slave (After Enable Edge)
t
HO
(M)
t
HO
(S)
0.25
0
t
CYC
(M)
ns
12
Rise time (20% V
DD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
RM
t
RS
100
2.0
ns
s
13
Fall time (70% V
DD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
FM
t
FS
100
2.0
ns
s
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