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参数资料
型号： MC68HC705C9ACP
厂商： Freescale Semiconductor
文件页数： 93/118页
文件大小： 0K
描述： IC MCU 2.1MHZ 16K OTP 40-DIP
标准包装： 9
系列： HC05
核心处理器： HC05
芯体尺寸： 8-位
速度： 2.1MHz
连通性： SCI，SPI
外围设备： POR，WDT
输入/输出数： 24
程序存储器容量： 16KB（16K x 8）
程序存储器类型： OTP
RAM 容量： 352 x 8
电压 - 电源 (Vcc/Vdd)： 3 V ~ 5.5 V
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 40-DIP（0.600"，15.24mm）
包装： 管件
Serial Peripheral Interface (SPI)
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
76
Freescale Semiconductor
10.5.2 Serial Peripheral Status Register
The SPI status register (SPSR), shown in Figure 10-5, contains flags to signal the following conditions:
SPI transmission complete
Write collision
Mode fault
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of data transfer between the
processor and external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is
generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an
access of the SPDR. Following the initial transfer, unless SPSR is read (with SPIF set) first, attempts
to write to SPDR are inhibited.
WCOL — Write Collision Bit
The write collision bit is set when an attempt is made to write to the serial peripheral data register while
data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer
ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin
the first time SCK becomes active while SS is low and the transfer ends when the SPIF flag gets set.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
to SPDR.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state. The MODF bit is normally
clear, and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects
the internal serial peripheral interface system in the following ways.
1.
An SPI interrupt is generated if SPIE = 1.
2.
The SPE bit is cleared. This disables the SPI.
3.
The MSTR bit is cleared, thus forcing the device into the slave mode.
Table 10-1. SPI Clock Rate Selection
SPR[1:0]
SPI Clock Rate
00
Internal Clock
÷ 2
01
Internal Clock
÷ 4
10
Internal Clock
÷ 16
11
Internal Clock
÷ 32
$000B
Bit 7
654321
Bit 0
Read:
SPIF
WCOL
MODF
Write:
Reset:
00000000
= Unimplemented
Figure 10-5. SPI Status Register
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