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参数资料
型号： MC68HC705JJ7S
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封装： WINDOWED, CERAMIC, DIP-20
文件页数： 142/164页
文件大小： 1165K
代理商： MC68HC705JJ7S
Analog Status Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
79
ISEN
The ISEN enable bit will power down the charge current source and disable the discharge device in
the analog subsystem. Powering down the current source will drop the supply current by about 200
A. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up the ramping current source and enables the discharge device on
the PB0/AN0 pin.
0 = Writing a logic 0 powers down the ramping current source and disables the discharge device on
the PB0/AN0 pin.
NOTE
The analog subsystem has support circuitry which draws current. This
current will be powered down if both comparators and the charge current
source are powered down (ISEN, CP1EN, and CP2EN all cleared).
Powering up either comparator or the charge current source will activate
the support circuitry.
8.4 Analog Status Register
The analog status register (ASR) contains status and control of the comparator flag bits. These bits in the
ASR are shown in Figure 8-6. All the bits in this register are cleared by a reset of the device.
CPF2
This read-only flag bit is edge sensitive to the rising output of comparator 2. It is set when the voltage
on the PB0/AN0 pin rises above the voltage on a sample capacitor which creates a positive edge on
the output of comparator 2, regardless of the state of the INV bit in the AMUX register. This bit is reset
by writing a logic 1 to the CPFR2 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 2 has occurred since the last time the CPF2
flag has been cleared.
0 = A positive transition on the output of comparator 2 has not occurred since the last time the CPF2
flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of comparator 1. It is set when the voltage
on the PB2/AN2 pin rises above the voltage on the PN3/AN3/TCAP pin which creates a positive edge
on the output of comparator 1, regardless of the state of the INV bit in the AMUX register. This bit is
reset by writing a logic 1 to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 1 has occurred since the last time the CPF1
flag has been cleared.
0 = A positive transition on the output of comparator 1 has not occurred since the last time the CPF1
flag has been cleared.
Address:
$001E
Bit 7
654321
Bit 0
Read:
CPF2
CPF1
0
COE1
VOFF
CMP2
CMP1
Write:
CPFR2
CPFR1
R
Reset:
00000000
= Unimplemented
R
= Reserved
Figure 8-6. Analog Status Register (ASR)
相关PDF资料
PDF描述
MC68HC705K1DWR2 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, MICROCONTROLLER, PDIP16
MC68HC705K1P 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1DW 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
MC68HC705KJ1CDW 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
相关代理商/技术参数
参数描述
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