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参数资料
| 型号： | MC68HC705P6ACP |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 24/98页 |
| 文件大小： | 532K |
| 代理商： | MC68HC705P6ACP |
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Operating Modes
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
30
Freescale Semiconductor
3.4.1.2 Halt Mode
NOTE
Halt mode is NOT designed for intentional use. Halt mode is only provided
to keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently. This mode of operation is usually achieved by
invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set places the MCU in this low-power
mode. Halt mode consumes the same amount of power as wait mode (both halt and wait modes consume
more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated
from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt mode and resume normal
operation. The halt mode also can be exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay of one to 4064 internal clock
cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization
delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode).
3.4.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which consumes more power than stop mode.
In wait mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated
from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal
operation. The 16-bit timer may be used to generate a periodic exit from wait mode. Wait mode may also
be exited when an IRQ external interrupt or RESET occurs.
3.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when the COP bit in the MOR is set.
Executing the STOP instruction when the SWAIT bit in the MOR is clear will cause the COP to be
disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (set
bit SWAIT in the MOR) if the COP watchdog timer is required to function at all times.
Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use
the wait mode for time periods that will exceed the COP timeout period.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC705P6ADW | 制造商:Rochester Electronics LLC 功能描述:MCU, 176 BYTES RAM, A/D - Bulk |
| MC68HC705P6AMDW | 功能描述:IC MCU 4.6K OTP 2.1MHZ 28-SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 标准包装:250 系列:56F8xxx 核心处理器:56800E 芯体尺寸:16-位 速度:60MHz 连通性:CAN，SCI，SPI 外围设备:POR，PWM，温度传感器，WDT 输入/输出数:21 程序存储器容量:40KB（20K x 16） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:6K x 16 电压 - 电源 (Vcc/Vdd):2.25 V ~ 3.6 V 数据转换器:A/D 6x12b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:48-LQFP 包装:托盘 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC705P6AMP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705P6CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705P6CP | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
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