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参数资料
| 型号： | MC68HC705P6ACP |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 32/98页 |
| 文件大小： | 532K |
| 代理商： | MC68HC705P6ACP |
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Input/Output Ports
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
38
Freescale Semiconductor
6.3 Port B
Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with the SIOP communications
subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is
located at address $0005. The contents of the port B data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin
to output mode (see Figure 6-2).
Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in
register SPCR is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port
B registers are still accessible to software. Writing to either of the port B registers while a data transfer is
under way could corrupt the data. See Chapter 7 Serial Input/Output Port (SIOP) for a discussion of the
SIOP subsystem.
Figure 6-2. Port B I/O Circuitry
6.4 Port C
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with the A/D subsystem. The port C
data register is located at address $0002 and its data direction register (DDR) is located at address
$0006. The contents of the port C data register are indeterminate at initial powerup and must be initialized
by user software. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the
port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see
Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in
register ADSC is used to enable/disable the A/D subsystem. Care must be exercised when using pins
PC0–PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3–PC7 in
the data or DDR registers will produce unpredictable results in the A/D subsystem. See Chapter 9 Analog
READ $0001
WRITE $0001
READ $0005
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0005
DATA DIRECTION
REGISTER BIT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC705P6ADW | 制造商:Rochester Electronics LLC 功能描述:MCU, 176 BYTES RAM, A/D - Bulk |
| MC68HC705P6AMDW | 功能描述:IC MCU 4.6K OTP 2.1MHZ 28-SOIC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 标准包装:250 系列:56F8xxx 核心处理器:56800E 芯体尺寸:16-位 速度:60MHz 连通性:CAN，SCI，SPI 外围设备:POR，PWM，温度传感器，WDT 输入/输出数:21 程序存储器容量:40KB（20K x 16） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:6K x 16 电压 - 电源 (Vcc/Vdd):2.25 V ~ 3.6 V 数据转换器:A/D 6x12b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:48-LQFP 包装:托盘 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC705P6AMP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705P6CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705P6CP | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
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