参数资料
型号: MC68HC705SR3PE
厂商: Freescale Semiconductor
文件页数: 57/96页
文件大小: 0K
描述: IC MCU 3.75K 2.1MHZ OTP 40-DIP
标准包装: 9
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 4MHz
外围设备: LED,POR
输入/输出数: 32
程序存储器容量: 3.75KB(3.75K x 8)
程序存储器类型: OTP
RAM 容量: 192 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 40-DIP(0.600",15.24mm)
包装: 管件
Freescale
8-6
MC68HC05SR3
CPU CORE AND INSTRUCTION SET
8
Table 8-3 Branch instructions
Relative addressing mode
Function
Mnemonic
Opcode # Bytes # Cycles
Branch always
BRA
20
2
3
Branch never
BRN
21
2
3
Branch if higher
BHI
22
2
3
Branch if lower or same
BLS
23
2
3
Branch if carry clear
BCC
24
2
3
(Branch if higher or same)
(BHS)
24
2
3
Branch if carry set
BCS
25
2
3
(Branch if lower)
(BLO)
25
2
3
Branch if not equal
BNE
26
2
3
Branch if equal
BEQ
27
2
3
Branch if half carry clear
BHCC
28
2
3
Branch if half carry set
BHCS
29
2
3
Branch if plus
BPL
2A
2
3
Branch if minus
BMI
2B
2
3
Branch if interrupt mask bit is clear
BMC
2C
2
3
Branch if interrupt mask bit is set
BMS
2D
2
3
Branch if interrupt line is low
BIL
2E
2
3
Branch if interrupt line is high
BIH
2F
2
3
Branch to subroutine
BSR
AD
2
6
Table 8-4 Bit manipulation instructions
Addressing modes
Bit set/clear
Bit test and branch
Function
Mnemonic
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
Branch if bit n is set
BRSET n (n=0–7)
2n
3
5
Branch if bit n is clear
BRCLR n (n=0–7)
01+2n
3
5
Set bit n
BSET n (n=0–7)
10+2n
2
5
Clear bit n
BCLR n (n=0–7)
11+2n
2
5
TPG
58
05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM
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