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| 型号： | MC68HC912BL16FU8 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | QFP-64 |
| 文件页数： | 34/128页 |
| 文件大小： | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16TS/D
13
In expanded wide mode, ports A and B are used for multiplexed 16-bit data and address buses. PA[7:0]
correspond to ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].
In expanded narrow mode, ports A and B are used for the 16-bit address bus, and an 8-bit data bus is
multiplexed with the most significant half of the address bus on port A. In this mode, 16-bit data is han-
dled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. PA[7:0]
correspond to ADDR[15:8] and to DATA[15:8] or DATA[7:0], depending on the bus cycle. The state of
the address pin should be latched at the rising edge of E. To allow for maximum address setup time at
external devices, a transparent latch should be used.
3.3.9 Read/Write (R/W)
In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of
reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until enabled.
3.3.10 Low-Byte Strobe (LSTRB)
In all modes this pin can be used as I/O and is a general-purpose input with an active pull-up out of
reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR reg-
ister. This signal is used in write operations and so external low byte writes will not be possible until this
function is enabled. This pin is also used as TAGLO in special expanded modes and is multiplexed with
the LSTRB function.
3.3.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
These signals are used to track the state of the internal instruction execution queue. Execution state is
time-multiplexed on the two signals. Refer to 16 Development Support.
3.3.12 Data Bus Enable (DBE)
The DBE pin (PE7) is an active low signal that will be asserted low during E-clock high time. DBE pro-
vides separation between output of a multiplexed address and the input of data. When an external ad-
dress is stretched, DBE is asserted during what would be the last quarter cycle of the last E-clock cycle
of stretch. In expanded modes this pin is used to enable the drive control of external buses during ex-
ternal reads only. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled
out of reset in expanded modes. This pin has an active pull-up during and after reset in single-chip
modes.
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