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| 型号： | MC68HC912BL16FU8 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | QFP-64 |
| 文件页数： | 37/128页 |
| 文件大小： | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16
16
MC68HC912BL16TS/D
When the PUPE bit in the PUCR register is set, PE[7,3,2, 1, 0] are pulled up. PE[7,3,2, 1, 0] are pulled
up active devices.
Neither port E nor DDRE is in the map in peripheral mode; neither is in the internal map in expanded
modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV
can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to 6 Bus
Control and Input/Output.
3.4.4 Port AD
Input to the analog-to-digital subsystem and general-purpose input. When analog-to-digital functions
are not enabled, the port has eight general-purpose input pins, PAD[7:0]. The ADPU bit in the ATDCTL2
register enables the A/D function.
Port AD pins are inputs; no data direction register is associated with this port. The port has no resistive
input loads and no reduced drive controls. Refer to 15 Analog-To-Digital Converter.
3.4.5 Port P
The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function
is enabled with the PWEN register. Enabling PWM pins takes precedence over the general-purpose
port. When pulse-width modulation is not in use, the port pins may be used for general-purpose I/O.
Register DDRP determines pin direction of port P when used for general-purpose I/O. When DDRP bits
are set, the corresponding pin is configured for output. On reset the DDRP bits are cleared and the cor-
responding pin is configured for input.
When the PUPP bit in the PWCTL register is set, all input pins are pulled up internally by an active pull-
up device. Pull-ups are disabled after reset.
Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels.
Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime
after reset. Refer to 11 Pulse-Width Modulator.
3.4.6 Port T
This port provides seven general-purpose I/O pins when not enabled for input capture and output com-
pare in the timer and pulse accumulator subsystem. The TEN bit in the TSCR register enables the timer
function. The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register.
Register DDRT determines pin direction of port T when used for general-purpose I/O. When DDRT bits
are set, the corresponding pin is configured for output. On reset the DDRT bits are cleared and the cor-
responding pin is configured for input.
When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pull-
up device. Pull-ups are disabled after reset.
Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels.
Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime
after reset. Refer to 12 Standard Timer Module.
3.4.7 Port S
Port S is the 6-bit interface to the standard serial interface consisting of the serial communications in-
terface (SCI) and serial peripheral interface (SPI) subsystems. Port S pins are available for general-pur-
pose parallel I/O when standard serial functions are not enabled.
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