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参数资料
| 型号： | MC68HC912BL16FU8 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | QFP-64 |
| 文件页数： | 98/128页 |
| 文件大小： | 3326K |
| 代理商： | MC68HC912BL16FU8 |
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MC68HC912BL16TS/D
71
PCLK0 — PWM Channel 0 Clock Select
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may
occur during the transition.
PPOL3 — PWM Channel 3 Polarity
0 = Channel 3 output is low at the beginning of the period; high when the duty count is reached.
1 = Channel 3 output is high at the beginning of the period; low when the duty count is reached.
PPOL2 — PWM Channel 2 Polarity
0 = Channel 2 output is low at the beginning of the period; high when the duty count is reached.
1 = Channel 2 output is high at the beginning of the period; low when the duty count is reached.
PPOL1 — PWM Channel 1 Polarity
0 = Channel 1 output is low at the beginning of the period; high when the duty count is reached.
1 = Channel 1 output is high at the beginning of the period; low when the duty count is reached.
PPOL0 — PWM Channel 0 Polarity
0 = Channel 0 output is low at the beginning of the period; high when the duty count is reached.
1 = Channel 0 output is high at the beginning of the period; low when the duty count is reached.
Depending on the polarity bit, the duty registers may contain the count of either the high time or the low
time. If the polarity bit is zero and left alignment is selected, the duty registers contain a count of the low
time. If the polarity bit is one, the duty registers contain a count of the high time.
NOTE
Register bits PCLK0 to PCLK3 may be written anytime. If a clock select is changed
while a PWM signal is being generated, a truncated or stretched pulse may occur
during transition.
NOTE
Depending on the polarity bit, the duty registers may contain the count of either the
high time or the low time. If the polarity bit is one, the output starts high and then
goes low when the duty count is reached, so the duty registers contatin a count of
the high time. If the polarity bits is zero, the output starts low and then goes high
when the duty count is reached, so the duty registers contatin a count of the low
time.
Setting any of the PWENx bits causes the associated port P line to become an output regardless of the
state of the associated data direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to zero, the data direction bit controls I/O direction. On the front end
of the PWM channel, the scaler clock is enabled to the PWM circuit by the PWENx enable bit being
high. When all four PWM channels are disabled, the prescaler counter shuts off to save power. There
is an edge-synchronizing gate circuit to guarantee that the clock will only be enabled or disabled at an
edge.
Read and write anytime.
PWEN3 — PWM Channel 3 Enable
The pulse modulated signal will be available at port P, bit 3 when its clock source begins its next cycle.
0 = Channel 3 is disabled.
PWEN — PWM Enable
$0042
Bit 7
6
5
4
3
2
1
Bit 0
0
PWEN3
PWEN2
PWEN1
PWEN0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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