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| 型号： | MC88915TFN55 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 1/18页 |
| 文件大小： | 401K |
| 代理商： | MC88915TFN55 |
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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MC88915T
Rev 6, 08/2004
Low Skew CMOS PLL Clock Drivers,
3-State
55, 70, 100, 133, and 160 MHz Versions
The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to
lock its low skew outputs frequencies and phase onto an input reference clock.
It is designed to provide clock distribution for high performance PCs and
workstations. For a 3.3 V version, see the MC88LV915T data sheet.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple components
on a board. The PLL also allows the MC88915T to multiply a low frequency
input clock and distribute it locally at a higher (2X) system frequency. Multiple
88915s can lock onto a single reference clock, ideal for applications when a
central system clock must be distributed synchronously to multiple boards
(see Figure 9).
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between
their rising edges. The Q5 output is inverted (180° phase shift) from the “Q”
outputs. The 2X_Q output runs at twice the “Q” output frequency, while the
Q/2 runs at 1/2 the “Q” frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q fmax
specification. The wiring diagrams in Figure 7 detail the different feedback
configurations, creating specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide-by in the feed-
back path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO
before its signal reaches the internal clock distribution section of the chip (see Figure 2. MC88915T Block Diagram (All Versions)). In
most applications FREQ_SEL should be held high (
÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2)
allows the VCO to run in its optimal range (>20 MHz and >40 MHz for the TFN133 version).
In normal phase-locked operation the PLL_EN pi is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915
in a static “test mode.” In this mode, there is no frequency limitation on the input clock, necessary for a low frequency board test en-
vironment. The second SYNC input can be used as a test clock input to further simplify board-level testing (see APPLICATIONS IN-
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5, and Q/2 into a high impedance state (3-state). After the
OE/RST pin goes back high Q0–Q4, Q5, and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go
low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915 sees a
SYNC signal and full 5.0 V VCC.
Features
Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD
specification, defining the part-to-part skew).
Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available
Input frequency range from 5 MHz – 2X_Q fmax specification (10 MHz – 2X_Q fmax for the TFN133 version)
Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL-level compatible. ±88 mA IOL/IOH specifications guarantee 50 transmission line switching on the incident edge.
Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All
outputs can go into high impedance (3-state) for board test purposes.
Lock indicator (LOCK) accuracy indicates a phase-locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
MC88915TFN55
MC88915TFN70
MC88915TFN100
MC88915TFN133
MC88915TFN160
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
LOW SKEW CMOS
PLL CLOCK DRIVER
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