参数资料
型号: MC88915TFN55
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 时钟及定时
英文描述: 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封装: PLASTIC, LCC-28
文件页数: 10/18页
文件大小: 401K
代理商: MC88915TFN55
MC88915T
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
43
Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board-to-Board Skew
MC88915T System Level Testing Functionality
Three-state functionality was added to the 100 MHz version
of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the
high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain in the low state
after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output is the inverse of the SYNC signal in this mode. If the
3-state functionality is used, a pull-up or pull-down resistor must
be tied to the FEEDBACK input pin to prevent it from floating
when the fed back output goes into high impedance.
With the PLL_EN pin low the selected SNC signal is gated
directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly
driven by the SYNC input (per the block diagram). This mode
can also be used for low frequency board testing.
NOTE: If the outputs are put into 3-state during normal PLL
operation, the loop will be broken and phase-lock will
be lost. It will take a maximum of 10 ms (tLOCK spec)
to regain phase-lock after the OE/RST pin goes back
high.
CMMU
CPU
CMMU
2f
PLL
MC88915T
CPU
CARD
CMMU
CPU
CMMU
2f
PLL
MC88915T
CPU
CARD
CLOCK
@ f
SYSTEM
CLOCK
SOURCE
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
AT POINT OF USE
MEMORY
CONTROL
2f
PLL
MC88915T
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
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相关代理商/技术参数
参数描述
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