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参数资料
| 型号： | MC88915TFN55 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 4/18页 |
| 文件大小： | 401K |
| 代理商： | MC88915TFN55 |
MC88915T
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
37
APPLICATIONS INFORMATION FOR ALL VERSIONS
General AC Specification Notes
1.
Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase-locked
operation. It is not possible to have the part in phase-lock
on automated test equipment (ATE). Statistical
characterization techniques were used to guarantee those
specifications which cannot be measured on the ATE.
MC88915TFN55, 70 and 100 units were fabricated with
key transistor properties intentionally varied to create a
14-cell designed experimental matrix. IC performance was
characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area, to set
performance limits of ATE testable specifications within
those to be guaranteed by statistical characterization. In
this way, all units passing the ATE test will meet or exceed
the non-tested specifications limits.
2.
These two specs (tRISE/FALL and tPULSE Width 2X_Q
output) guarantee the MC88915T meets the 40 MHz and
33 MHz MC68040 P-Clock input specification (at 80 MHz
and 66 MHz, respectively). For these two specs to be
guaranteed by Freescale Semiconductor, the termination
scheme shown below in Figure 3 must be used.
3.
The wiring diagrams and explanations in Figure 7
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 22 below summarizes the allowable SYNC
frequency range for each possible configuration.
Figure 3. MC68040 P-Clock Input Termination Scheme
4.
A 1 M
resistor tied to either Analog VCC or Analog GND,
depicted in Figure 4, is required to ensure no jitter is
present on the MC88915T outputs. This technique causes
a phase offset between the SYNC input and the output
connected to the FEEDBACK input, measured at the input
pins. The tPD spec describes how this offset varies with
process, temperature, and voltage. The specs were
determined by measuring the phase relationship for the
14 lots described in Note 1 while the part was in
phase-locked operation. The actual measurements were
made with a 10 MHz SYNC input (1.0 ns edge rate from
0.8 V – 2.0 V) with the Q/2 output fed back. The phase
measurements were made at 1.5 V. The Q/2 output was
terminated at the FEEDBACK input with 100
to VCC and
100
to ground.
Table 22. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHz)
Corresponding VCO
Frequency Range
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
HIGH
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
0°
180°
0°
LOW
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
0°
180°
0°
88915
2X_Q OUTPUT
RS
RS = ZO – 7
RP
ZO (CLOCK TRACE)
RP = 1.5 ZO
68040
P-CLOCK INPUT
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相关代理商/技术参数 |
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| MC88915TFN70R2 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MC88916 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| MC88916DW | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| MC88916DW70 | 功能描述:IC DRIVER CLK PLL 70MHZ 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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