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参数资料
| 型号： | MC88915TFN55 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 8/18页 |
| 文件大小： | 401K |
| 代理商： | MC88915TFN55 |
MC88915T
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
41
Figure 7. Wiring Diagrams
FEEDBACK
REF_SEL
SYNC[0]
ANALOG VCC
RC1
ANALOG GND
FQ_SEL Q0
Q1 PLL_EN
HIGH
RST
Q5
Q4
2X_Q
Q/2
Q3
Q2
LOW
25 MHz INPUT
EXTERNAL
LOOP
FILTER
100 MHz SIGNAL
25 MHz FEEDBACK SIGNAL
HIGH
50 MHz
“Q” CLOCK
OUTPUTS
CRYSTAL
OSCILLATOR
FEEDBACK
REF_SEL
SYNC[0]
ANALOG VCC
RC1
ANALOG GND
FQ_SEL Q0
Q1 PLL_EN
HIGH
RST
Q5
Q4
2X_Q
Q/2
Q3
Q2
LOW
50 MHz INPUT
EXTERNAL
LOOP
FILTER
100 MHz SIGNAL
50 MHz FEEDBACK SIGNAL
HIGH
50 MHz
“Q” CLOCK
OUTPUTS
CRYSTAL
OSCILLATOR
25 MHz
SIGNAL
FEEDBACK
REF_SEL
SYNC[0]
ANALOG VCC
RC1
ANALOG GND
FQ_SEL Q0
Q1 PLL_EN
HIGH
RST
Q5
Q4
2X_Q
Q/2
Q3
Q2
LOW
100 MHz INPUT
EXTERNAL
LOOP
FILTER
100 MHz FEEDBACK SIGNAL
HIGH
50 MHz
“Q” CLOCK
OUTPUTS
CRYSTAL
OSCILLATOR
25 MHz
SIGNAL
MC88915T
Figure 7a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback
Figure 7b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback
Figure 7c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feedback
1:2 Input to “Q” Output Frequency Relationship
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
Allowable Input Frequency Range:
5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
NOTE: If the OE/RST input is active, a pullup or pull-down
resistor isn’t necessary at the FEEDBACK pin so it won’t
when the fed back output goes into 3-state.
1:1 Input to “Q” Output Frequency Relationship
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
Allowable Input Frequency Range:
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
equal the SYNC frequency. The Q/2 output will
always rn at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
2:1 Input to “Q” Output Frequency Relationship
In this application, the 2X_Q output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
Allowable Input Frequency Range:
20 MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
The Q/2 output will always run at 1/3 the 2X_Q
frequency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
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