参数资料
型号: MC9328MX21CVK
厂商: Freescale Semiconductor
文件页数: 93/100页
文件大小: 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
标准包装: 152
系列: i.MX21
核心处理器: ARM9
芯体尺寸: 32-位
速度: 266MHz
连通性: 1 线,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 192
程序存储器类型: ROMless
电压 - 电源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 289-LFBGA
包装: 托盘
MC9328MX21 Technical Data, Rev. 3.4
92
Freescale Semiconductor
Specifications
3.21
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 80. Definition of Bus Timing for I2C
3.22
CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32
× 32 image data receive FIFO, and a 16 × 32
statistic data FIFO.
3.22.1
Gated Clock Mode
Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 82 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 45. The formula for
calculating the pixel clock rise and fall time is located in Section 3.22.3, “Calculation of Pixel Clock Rise/
Table 44. I2C Bus Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.1 V
3.0 V
± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
0
100
0
100
kHz
1
Hold time (repeated) START condition
114.8
111.1
ns
2
Data hold time
0
69.7
0
72.3
ns
3
Data setup time
3.1
1.76
ns
4
HIGH period of the SCL clock
69.7
68.3
ns
5
LOW period of the SCL clock
336.4
335.1
ns
6
Setup time for STOP condition
110.5
111.1
ns
SDA
SCL
1
2
3
4
6
5
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