参数资料
型号: MC9RS08KA1CSCR
厂商: Freescale Semiconductor
文件页数: 72/136页
文件大小: 0K
描述: IC MCU 8-BIT 1K FLASH 8-SOIC
产品培训模块: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
标准包装: 1
系列: RS08
核心处理器: RS08
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,WDT
输入/输出数: 4
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 63 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
产品目录页面: 726 (CN2011-ZH PDF)
其它名称: MC9RS08KA1CSCRDKR
Chapter 5 Resets, Interrupts, and General System Control
MC9RS08KA2 Series Data Sheet, Rev. 4
40
Freescale Semiconductor
5.8.3
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the RS08
derivative and revision number. This allows the development software to recognize where specific
memory blocks, registers, and control bits are located in a target MCU.
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-3. System Device Identification Register — High (SDIDH)
Table 5-3. SOPT Register Field Descriptions
Field
Description
7
COPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE1,2
1 When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is
disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active
BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.
2 BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be
changed back to 1 only by a POR or reset with proper condition as stated in Note 1.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO.
1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/VPP pin to function
as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA2/KBIP2/TCLK/RESET/VPP pin functions as PTA2/KBIP2/TCLK/VPP.
1 PTA2/KBIP2/TCLK/RESET/VPP pin functions as RESET/VPP.
76
54
321
0
R
W
Reset:
0 (Note 1)
1
0
= Unimplemented or Reserved
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