参数资料
型号: MCIMX251AJM4A
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封装: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件页数: 124/140页
文件大小: 1416K
代理商: MCIMX251AJM4A
i.MX25 Applications Processor for Automotive Products, Rev. 8
84
Freescale Semiconductor
3.7.8
Enhanced Secured Digital Host Controller (eSDHCv2) Timing
Figure 54 shows eSDHCv2 timing, and Table 61 describes the timing parameters (SD1–SD8) used in the
figure. The following definitions apply to values and signals described in Table 61:
LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz
FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card
clock can reach 25 MHz
HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can
reach 50 MHz
86
SCKT rising edge to data out valid
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high
impedance6
——
21.0
16.0
x ck
i ck
ns
88
SCKT rising edge to transmitter #0 drive
enable negation6
——
14.0
9.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT
falling edge5
——
2.0
18.0
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling
edge
——
2.0
18.0
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
4.0
5.0
x ck
i ck
ns
92
FST input (wl) to data out enable from high
impedance
——
21.0
ns
93
FST input (wl) to transmitter #0 drive enable
assertion
——
14.0
ns
94
Flag output valid after SCKT rising edge
14.0
9.0
x ck
i ck
ns
95
HCKR/HCKT clock cycle
2 x TC
15
ns
96
HCKT input rising edge to SCKT output
18.0
ns
97
HCKR input rising edge to SCKR output
18.0
ns
1 V
CORE_VDD = 1.00 ± 0.10 V; TJ = –40 °C to 125 °C, CL = 50 pF
2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative
3 In the “Expression” column, T
C = 7.5 ns.
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal),
until the second-to-last bit-clock of the first word in the frame.
6 Periodically sampled and not 100% tested.
Table 60. ESAI General Timing Requirements (continued)
No.
Characteristics1 2
Symbol
Expression3
Min.
Max.
Condition
Unit
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MCIMX251AVM4 功能描述:处理器 - 专门应用 SENNA IMX25 1.1 AUTO RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
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