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参数资料
型号： MCIMX31VMN5CR2
厂商： Freescale Semiconductor
文件页数： 37/122页
文件大小： 0K
描述： IC MPU MAP I.MX31L 473-MAPBGA
标准包装： 750
系列： i.MX31
核心处理器： ARM11
芯体尺寸： 32-位
速度： 532MHz
连通性： 1 线，ATA，EBI/EMI，FIR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外围设备： DMA，LCD，POR，PWM，WDT
程序存储器类型： ROMless
RAM 容量： 16K x 8
电压 - 电源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 473-LFBGA
包装： 带卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
21
Figure 3. Option 1 Power-Up Sequence (Silicon Revision 2.0)
Figure 4. Option 2 Power-Up Sequence (Silicon Revision 2.0)
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
Hold POR Asserted
1
1, 2
1, 3, 5
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
3
The parallel paths in the flow indicate that supply group
NVCC2, NVCC21, and NVCC22, and supply group
FVCC, MVCC, SVCC, and UVCC ramp-ups are
independent. Note that this power-up sequence is
backward compatible to Silicon Revs. 1.15 and 1.2,
because NVCC2x ramp-up proceeding PLL supplies is
allowed.
4
Unlike the power-up sequence for Silicon Revision 1.2,
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
5
Raising IOQVDD before NVCC21 produces a slight
increase in current drain on IOQVDD of approximately
3–5 mA. The current increase will not damage the IC.
Refer to Errata ID TLSbo91750 for details.
FVCC, MVCC, SVCC, UVCC
1,3
4
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22
Hold POR Asserted
1
1, 2,3
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
3
Raising NVCC2, NVCC21, and NVCC22 at the same
time as IOQVDD does not produce the slight increase in
current drain on IOQVDD (as described in Figure 3,
Note 5).
4
Unlike the power-up sequence for Silicon Revision 1.2,
FUSE_VDD should not be driven on power-up for Silicon
Revision 2.0. This supply is dedicated for fuse burning
(programming), and should not be driven upon boot-up.
FVCC, MVCC, SVCC, UVCC
1
4
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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