参数资料
型号: MCIMX31VMN5CR2
厂商: Freescale Semiconductor
文件页数: 81/122页
文件大小: 0K
描述: IC MPU MAP I.MX31L 473-MAPBGA
标准包装: 750
系列: i.MX31
核心处理器: ARM11
芯体尺寸: 32-位
速度: 532MHz
连通性: 1 线,ATA,EBI/EMI,FIR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外围设备: DMA,LCD,POR,PWM,WDT
程序存储器类型: ROMless
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 473-LFBGA
包装: 带卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
61
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 46. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 47 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 47. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 48 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
DISPB_D3_CLK
12
3
m
m-1
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_CLK
IP7
IP9
IP10
IP8
Start of line
IP5
IP6
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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