参数资料
型号: MCIMX357DVM5BR2
厂商: Freescale Semiconductor
文件页数: 98/147页
文件大小: 0K
描述: IC MPU I.MX35 400MAPBGA
标准包装: 1,000
系列: i.MX35
核心处理器: ARM11
芯体尺寸: 32-位
速度: 532MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 96
程序存储器类型: ROMless
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振荡器型: 外部
工作温度: -20°C ~ 70°C
封装/外壳: 400-LFBGA
包装: 带卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
54
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value. DDR SDRAM CLK parameters are measured at the
crossing point of SDCLK and SDCLK (inverted clock).
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended
drive strength is Medium for SDCLK and High for Address and controls.
Figure 34. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 43. DDR2 SDRAM Read Cycle Parameter Table
ID
PARAMETER
Symbol
DDR2-400
Unit
Min
Max
DDR24
DQS – DQ Skew (defines the Data valid window in
read cycles related to DQS).
tDQSQ
—0.35
ns
DDR25
DQS DQ in HOLD time from DQS1
1The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =
0.45
× tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.
tQH
2.925
ns
DDR26
DQS output access time from SDCLK posedge
tDQSCK
–0.5
0.5
ns
Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters1
1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
Parameter
Symbol
Min.
Max.
Unit
SD17
DQ and DQM setup time to DQS
tDS
0.95
ns
SD18
DQ and DQM hold time to DQS
tDH
0.95
ns
SD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
1.8
ns
SD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
1.8
ns
SDCLK
DQS (output)
DQ (output)
DQM (output)
Data
DM
SD17
SD18
SD19
SD20
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