参数资料
| 型号： | MCP662-E/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 14/62页 |
| 文件大小： | 0K |
| 描述： | IC OP AMP 60MHZ DUAL 8-MSOP |
| 标准包装： | 100 |
| 放大器类型： | 通用 |
| 电路数： | 2 |
| 输出类型： | 满摆幅 |
| 转换速率： | 32 V/µs |
| 增益带宽积： | 60MHz |
| 电流 - 输入偏压： | 6pA |
| 电压 - 输入偏移： | 1800µV |
| 电流 - 电源： | 6mA |
| 电流 - 输出 / 通道： | 80mA |
| 电压 - 电源，单路/双路(±)： | 2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
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2009-2011 Microchip Technology Inc.
DS22194C-page 21
MCP660/1/2/3/4/5/9
4.0
APPLICATIONS
The MCP660/1/2/3/4/5/9 family is manufactured using
the Microchip state-of-the-art CMOS process. It is
designed for low-cost, low-power and high-speed
applications. Its low supply voltage, low quiescent cur-
rent and wide bandwidth make the MCP660/1/2/3/4/5/9
ideal for battery-powered applications.
4.1
Input
4.1.1
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply volt-
ages. Figure 2-39 shows an input voltage exceeding
both supplies with no phase inversion.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The electrostatic discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors,
and to minimize input bias current (IB). The input ESD
diodes clamp the inputs when they try to go more than
one diode drop below VSS. They also clamp any
voltages that go too far above VDD; their breakdown
voltage is high enough to allow normal operation, and
low enough to bypass quick ESD events within the
specified limits.
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN-) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN-) from going too far above VDD, and
dump any currents onto VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
FIGURE 4-2:
Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (VCM) is below ground (VSS); see
Figure 2-13. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3
NORMAL OPERATION
The input stage of the MCP660/1/2/3/4/5/9 op amps
use a differential PMOS input stage. It operates at low
Common mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured at
5 and Figure 2-6 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
FIGURE 4-3:
Unity Gain Voltage
Limitations for Linear Operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN-
V1
R1
VDD
D1
R1 >
VSS – (minimum expected V1)
2 mA
VOUT
R2 >
VSS – (minimum expected V2)
2 mA
V2
R2
D2
MCP66X
VIN
VDD
VOUT
V
SS
V
<
IN
V
,
OUT
V
DD
1.3V
–
≤
MCP66X
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