参数资料
型号: MCZ33780EG
厂商: Freescale Semiconductor
文件页数: 34/37页
文件大小: 0K
描述: IC MASTER DUAL DBUS DIFF 16-SOIC
标准包装: 47
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
安装类型: 表面贴装
产品目录页面: 808 (CN2011-ZH PDF)
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
33780
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Output Signal Low Voltage (Differential)
-12.5 mA
≤ InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA (5)
VDnD(LOW)
1.175
1.5
1.825
V
Vmid, (DnH + DnL)/2 (Voltage Halfway Between Bus High Side and
Bus Low Side)
Vmid
VSUP/2 -
1.0
VSUP/2
VSUP/
2 +1.0
V
VCM Peak-to-Peak, Vmid (Signal High) - Vmid (Signal Low)
VCMpp
0.3
V
Output High-Side (DnH) Idle Driver Current Limit (DnL open)
Source: DnH = 0 V
Sink: DnH = VSUP
IICL(HIGH)
-400
100
-200
mA
Output Low-Side (DnL) Idle Driver Current Limit (DnH open)
Source: DnL = 0 V
Sink: DnL = VSUP
IICL(LOW)
200
-100
400
mA
Output High-Side (DnH) Signal Driver Overcurrent Shutdown
Source: Signal High, Signal Low
Sink: Signal High, Signal Low
ISCL(HIGH)
-100
30
-30
100
mA
Output Low-Side (DnL) Signal Driver Overcurrent Shutdown
Source: Signal High, Signal Low
Sink: Signal High, Signal Low
ISCL(LOW)
-100
30
-30
100
mA
Disabled High-Side (DnH) Bus Leakage (DnL open)
DnH = 0 V
DnH = VSUP
ILK(HIGH)
-1.0
-0.18
0.25
1.0
mA
Disabled Low-Side (DnL) Bus Leakage (DnH open)
DnL = 0 V
DnL = VSUP
ILK(LOW)
-1.0
-0.4
0.08
1.0
mA
BUS RECEIVER (D0H, D0L, D1H, D1L)
Comparator Trip Point
COMP(TRIP)
5.0
6.0
7.0
mA
Notes
7
Not measured in production.
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V
≤ V
CC ≤ 5.25 V, 9.0 V ≤ VSUP ≤ 25 V,-40°C ≤ T
A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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