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| 型号： | MCZ33780EG |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 8/37页 |
| 文件大小： | 0K |
| 描述： | IC MASTER DUAL DBUS DIFF 16-SOIC |
| 标准包装： | 47 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 808 (CN2011-ZH PDF) |
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Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The DSIF signal controls the state of the drivers, enabling
the Idle drivers or Signal drivers as is appropriate. A
comparator in the Control block compares the DnL output
voltage with the internal Signal high voltage to determine the
transition from Idle driver to Signal driver. The overvoltage
signal modifies the driver characteristics. This is described in
more detail in the Load Dump Operation section.
The overtemperature signal is also applied to this block.
The Differential Signal Generation block converts the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
the Signal drivers. This block is active in all driver modes.
A special requirement of the differential bus is to maintain
a low common mode voltage. This is especially important
during the Idle to Signal transition in order to produce a
smooth changeover to the Signal driver. This is accomplished
by monitoring the common mode voltage and modifying the
Idle driver slew rates. This is the function of the Common
Mode Correction block. An additional feature to make a
smooth changeover and minimize undershoot is to reduce
the slew rate as the changeover point is approached. This
block is not illustrated in Figure 10.
A sense resistor between the Signal driver and the DnH
output detects the Slave device response current. A
comparator (Comp.) generates the signal DSIR that is
supplied to the logic.
The comparator consists of a sense amplifier with offset
(VOS), a filter capacitor and logic gate with buffers to produce
the logic signal (DSIR). The sense amplifier is a ‘gm’ stage
that amplifies the voltage across the sense resistor (RS) to
produce an output current that charges and discharges a filter
capacitor. The voltage across the filter capacitor is compared
with the threshold voltage of the logic gate to produce the
output signal. The voltage across the filter capacitor is
clamped between VCC and ground. See Figure 11.
Figure 11. Receive Filter
Definitions
C = value of filter capacitor = 2.0 pF
VTH = threshold of logic gate = VCC/2 = 2.5 V
A = current gain from sense resistor to filter capacitor =
IO/IBUS = 3.0 A/mA (the amplifier saturates with an
output current of ±40
A)
IBUS[mA] = bus response current.
ITH[mA] = response current threshold = VOS/RS = 6
The filter delay time is given by:
t[
s] = (C * V
TH) / A (IBUS - ITH) = 1.7 / (IBUS- ITH)
The filter characteristic can also be expressed as the
product of the overdrive current (IBUS-ITH) and the duration of
the interference pulse, which must be less than 1.7
s * mA
for the interference to be filtered.
DnH
DSIR
IBUS
RS
VOS
IO
C
gm
VTH
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCZ33780EG | 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC |
| MCZ33780EGR2 | 功能描述:多路器开关 IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
| MCZ33781EK | 功能描述:输入/输出控制器接口集成电路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| MCZ33781EKR2 | 功能描述:输入/输出控制器接口集成电路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| MCZ33784EF | 功能描述:加速计 - 板上安装 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 传感轴:Double 加速:12 g 灵敏度: 封装 / 箱体: 输出类型:Analog 数字输出 - 位数:11 bit 电源电压-最大:5.25 V 电源电压-最小:4.75 V 电源电流:4 mA 最大工作温度:+ 125 C 最小工作温度:- 40 C |
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