参数资料
型号: MCZ33800EK
厂商: Freescale Semiconductor
文件页数: 13/39页
文件大小: 0K
描述: IC ENGINE CTRL SW/DVR 54-SOIC
标准包装: 26
应用: 自动
电流 - 电源: 10mA
电源电压: 5 V ~ 36 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 管件
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ V DD ≤ 5.5V, 9.0V ≤ V PWR ≤ 18V, - 40 ° C ≤ T A ≤ 125 ° C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED)
Output Off Open Circuit Fault Filter Timer (11)
t OC
400
500
650
μ s
Output Slew Rate
V/ μ s
R LOAD = 51 ?
R LOAD = 51 ?
t SR(RISE)
t SR(FALL)
1.0
1.0
5.0
5.0
10
10
P1 Input Propagation Delay
μ s
Input @ 50% V DD to Output voltage 10% of final value
Input @ 50% V DD to Output voltage 90% of initial value
P3, P5, P7 Input Propagation Delay
Input @ 50% V DD to Output voltage 10% of final value
Input @ 50% V DD to Output voltage 90% of initial value
OSCILLATOR AND TIMER ACCURACY
t (RISEDELAY)
t (FALLDELAY)
t (RISEDELAY)
t (FALLDELAY)
6.0
6.0
5.0
5.0
μ s
Calibrated Timer Accuracy (11)
Un-calibrated Timer Accuracy
t TIMER
t TIMER
± 10
± 80
%
%
SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)
(12)
Required Low State Duration on V PWR for Reset (13)
t RESET
μ s
V PWR ≤ 0.2V
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
Rising Edge of SCLK to SI
Required Hold Time
t LEAD
t LAG
t SI (SU)
t SI (HOLD)
1.0
100
50
16
20
ns
ns
ns
ns
SI, CS , SCLK Signal Rise Time (14)
t R (SI)
5.0
ns
SI, CS , SCLK Signal Fall Time
(14)
t F (SI)
5.0
ns
Time from Falling Edge of CS to SO
Low-impedance (15)
t SO (EN)
150
ns
Time from Rising Edge of CS to SO High-impedance
(16)
t SO (DIS)
150
ns
Time from Falling Edge of SCLK to SO Data Valid
(17)
t VALID
25
150
ns
Sequential Transfer Rate
t STR
1.0
μ s
Time required between data transfers
Notes
11.
12.
13.
14.
15.
16.
17.
Assumes oscillator has been calibrated using SPI Calibrate Command
These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI, CS , and SCLK signals for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
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