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| 型号： | MCZ33800EK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/39页 |
| 文件大小： | 0K |
| 描述： | IC ENGINE CTRL SW/DVR 54-SOIC |
| 标准包装： | 26 |
| 应用： | 自动 |
| 电流 - 电源： | 10mA |
| 电源电压： | 5 V ~ 36 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 54-SOICW-EP |
| 包装： | 管件 |
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PIN CONNECTIONS
PIN CONNECTIONS
VDSNS4
GD4
VDSNS5
GD5
VDSNS6
GD6
VSSNS456
LRFDBK
SI
SCLK
CS
P1
P3
P5
P7
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CCD2_GND
CCD2_OUT
CCD2_REC
EN
RI_REF
CCD1_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDSNS3
GD3
VDSNS2
GD2
VDSNS1
GD1
VSSNS123
REXT
PGND1
OUT1
PGND2
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
OUT8
DEFAULT
SO
VDD
VCAL
GND
VPWR
CCD1_GND
CCD1_REC
Figure 3. 33800 Pin Connections
Table 1. 33800 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16 .
Pin Number
1, 3, 5, 50,
52, 54
2, 4, 6, 49,
Pin Name
VDSNS1-
VDSNS6
GD1-GD6
Pin Function
Input
Output
Formal Name
Drain Voltage Sense
Gate Driver Output
Definition
The VDSNS pin is used to monitor the drain voltage of the external
MOSFET.
The GD pin provides gate drive for an external MOSFET
51, 53
7
48
VSSNS456
VSSNS123
Input
Source Voltage Sense The VSSNS pins are used to monitor the source voltage of the external
MOSFETS.
8
LRFDBK
Output
Load Resistance
The LRFDBK pin is an operational amplifier output.
Feedback
9
SI
Input
Serial Input Data
The SI input pin is used to receive serial data from the MCU. The serial
input data is latched on the rising edge of SCLK, and the input data
transitions on the falling edge of SCLK.
10
SCLK
Input
Serial Clock Input
The SCLK input pin is used to clock in and out the serial data on the SI
and SO Pins while being addressed by the CS.
11
CS
Input
Chip Select
The Chip Select input pin is an active low signal sent by the MCU to
indicate that the device is being addressed. This input requires CMOS
logic levels and has an internal active pull up current source.
12
P1
Input
Input One
Input control of OSS output 1. When configured via the SPI, P1 input may
be used to control OSS output 1 and output 2 in parallel.
13
P3
Input
Input Three
Input control of OSS output 3. When configured via the SPI, P3 input may
be used to control OSS output 3 and output 4 in parallel.
14
P5
Input
Input Five
Input control of OSS output 5. When configured via the SPI, P5 input may
be used to control OSS output 5 and output 6 in parallel.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
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