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| 型号： | MCZ33937EK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/48页 |
| 文件大小： | 0K |
| 描述： | IC PRE-DRIVER 3PHASE 54-SOIC |
| 标准包装： | 26 |
| 系列： | SMARTMOS™ |
| 配置： | 3 相桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 265ns |
| 电流 - 峰： | 600mA |
| 配置数： | 1 |
| 输出数： | 3 |
| 高端电压 - 最大（自引导启动）： | 15V |
| 电源电压： | 8 V ~ 40 V |
| 工作温度： | -40°C ~ 135°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 54-SOICW-EP |
| 包装： | 管件 |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V ? V PWR = V SUP ? 40 V, -40 ? C ? T A ? 135 ? C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INTERNAL REGULATORS
V DD Power-up Time (Until INT High)
t PU_VDD
ms
8.0 V ?? V PWR
(36) , (43)
–
–
2.0
VLS Power-up Time
t PU_VLS
ms
16 V ?? V PWR
(37) , (43)
–
–
2.0
CHARGE PUMP
Charge Pump Oscillator Frequency
Charge Pump Slew Rate (38)
F OSC
SR CP
90
–
125
100
190
–
kHz
V/μs
GATE DRIVE
High Side Turn On Time (39)
t ONH
ns
Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, ( Figure 7 )
High Side Turn On Delay (40)
Delay from Command to 1.0 V, ( Figure 7 )
High Side Turn Off Time (39)
Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, ( Figure 8 )
High Side Turn Off Delay (40)
Delay from Command to 10 V, ( Figure 8 )
Low Side Turn On Time (39)
Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, ( Figure 7 )
Low Side Turn On Delay (40)
Delay from Command to 1.0 V, ( Figure 7 )
Low Side Turn Off Time (39)
Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, ( Figure 8 )
Low Side Turn Off Delay (40)
Delay from Command to 10 V, ( Figure 8 )
t D_ONH
t OFFH
t D_OFFH
t ONL
t D_ONL
t OFFL
t D_OFFL
–
130
–
130
–
130
–
130
20
265
20
265
20
265
20
265
35
386
35
386
35
386
35
386
ns
ns
ns
ns
ns
ns
ns
Same Phase Command Delay Match (41)
Thermal Filter Duration (42)
t D_DIFF
t DUR
-20
8.0
0.0
–
+20
30
ns
μs
Notes
36. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on V DD .
37.
38.
39.
40.
41.
42.
43.
The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and
VLS_CAP. This delay includes the expected time for V DD to rise.
The charge pump operating at 12 V V SYS , 1.0 ? F pump capacitor, MUR120 diodes and 47 μF filter capacitor.
This parameter is guaranteed by characterization, not production tested.
These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes
one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and
output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision
block. Synchronization time accounts for up to one clock period of variation. See Figure 6 .
The maximum separation or overlap of the High and Low Side gate drives, due to propagation delays when commanding one ON and
the other OFF simultaneously, is guaranteed by design.
The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
This specification is based on capacitance of 0.47 μF on VDD, 2.2 μF on VLS and 2.2 μF on VLS_CAP.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
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