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| 型号： | MCZ33937EK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/48页 |
| 文件大小： | 0K |
| 描述： | IC PRE-DRIVER 3PHASE 54-SOIC |
| 标准包装： | 26 |
| 系列： | SMARTMOS™ |
| 配置： | 3 相桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 265ns |
| 电流 - 峰： | 600mA |
| 配置数： | 1 |
| 输出数： | 3 |
| 高端电压 - 最大（自引导启动）： | 15V |
| 电源电压： | 8 V ~ 40 V |
| 工作温度： | -40°C ~ 135°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 54-SOICW-EP |
| 包装： | 管件 |
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ? V PWR = V SUP ? 40 V ?? -40 ? C ? T A ? 135 ? C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CHARGE PUMP
Charge Pump
High Side Switch On Resistance
Low Side Switch On Resistance
Regulation Threshold Difference (15) , (17)
R DS(on)_HS
R DS(on)_LS
V THREG
–
–
250
6.0
5.0
500
10
9.4
900
?
?
mV
Charge Pump Output Voltage (16) , (17)
V CP
V
I OUT = 40 mA, 6.0 V < V SYS < 8.0 V
I OUT = 40 mA, V SYS > = 8.0 V
8.5
12
9.5
–
–
–
GATE DRIVE
High Side Driver On Resistance (Sourcing)
R DS(ON)_H_SRC
?
V PWR = V SUP = 16 V, -40 ? C ? T A ? 25 ? C
V PWR = V SUP = 16 V, 25 ? C ?? T A ? 135 ? C
High Side Driver On Resistance (Sinking)
V PWR = V SUP = 16 V
R DS(ON)_H_SINK
–
–
–
–
–
–
6.0
8.5
3.0
?
High Side Current Injection Allowed Without Malfunction (17) , (18)
I HS_INJ
–
–
0.5
A
Low Side Driver On Resistance (Sourcing)
R DS(ON)_L_SRC
?
V PWR = V SUP = 16 V, -40 ? C ? T A ? 25 ? C
V PWR = V SUP = 16 V, 25 ? C ?? T A ? 135 ? C
Low Side Driver On-Resistance (Sinking)
V PWR = V SUP = 16 V
R DS(ON)_L_SINK
–
–
–
–
–
–
6.0
8.5
3.0
?
Low Side Current Injection Allowed Without Malfunction (17) , (18)
I LS_INJ
–
–
0.5
?
Gate Source Voltage, V PWR = V SUP = 40 V
V
High Side, I GATE =
0 (19)
V GS_H
13
14.8
16.5
Low Side, I GATE = 0
Reverse High Side Gate Holding
Voltage (20)
V GS_L
V HS_G_HOLD
13
15.4
17
V
Gate Output Holding Current = 2.0 μA
Gate Output Holding Current = 5.0 μA, V SUP <26 V
Gate Output Holding Current = 5.0 μA, V SUP <40 V
–
–
–
10
10
–
15
15
15
Notes
15. When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled.
16. V SYS is the system voltage on the input to the charge pump. Recommended external components: 1.0 μF MLC, MUR 120 diode.
17.
18.
19.
20.
This parameter is a design characteristic, not production tested.
Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of
approximately 1.0 μs after an output switch transition. 1.0 μs is sufficient for all intended applications of this IC.
If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not
recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap
and the VLS capacitors.
High Side Gate Holding voltage is the voltage between the Gate and Source of the high side FET when held in an on condition. The
trickle charge pump supplies bias and holding current for the High Side FET gate driver and output to maintain voltages after bootstrap
events. See Figure 11 for typical 100% high side gate voltage with a 5.0 μA load. This parameter is a design characteristic, not
production tested.
33937A
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
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