参数资料
型号: MCZ33937EK
厂商: Freescale Semiconductor
文件页数: 22/48页
文件大小: 0K
描述: IC PRE-DRIVER 3PHASE 54-SOIC
标准包装: 26
系列: SMARTMOS™
配置: 3 相桥
输入类型: 非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 15V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 管件
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
allow pulses of current to flow in the external FET. This output
has also been designed to resist the influence of negative
currents.
PHASE C HIGH SIDE SOURCE (PC_HS_S)
The source connection for the Phase C high side output
FET is the reference voltage for the gate drive on the high
side FET and also the low-voltage end of the bootstrap
capacitor.
PHASE C HIGH SIDE GATE (PC_HS_G)
This is the gate drive for the Phase C high side output FET.
This pin provides the gate bias to turn the external FET on or
off. The gate voltage is limited to about 15 V above the FET
source voltage. A low-impedance drive is used, ensuring
transient currents do not overcome an off-state driver and
allow pulses of current to flow in the external FETs. This
output has also been designed to resist the influence of
negative currents.
PHASE C BOOTSTRAP (PC_BOOT)
This is the bootstrap capacitor connection for Phase C. A
capacitor connected between PC_HS_S and this pin
provides the gate voltage and current to drive the external
FET gate. Typically, the bootstrap capacitor selection is 10 to
20 times the gate capacitance. The voltage across this
capacitor is limited to about 15 V.
PHASE B LOW SIDE SOURCE (PB_LS_S)
The Phase B low side source is the pin used to return the
gate currents from the Low Side FET. Best performance is
realized by connecting this node directly to the source of the
low side FET for Phase B.
PHASE B LOW SIDE GATE (PC_LS_G)
This is the gate drive for the Phase B low side output FET.
It provides high-current through a low-impedance to turn on
and off the low side FET. A low-impedance drive ensures
transient currents do not overcome an off-state driver and
allow pulses of current to flow in the external FET. This output
has also been designed to resist the influence of negative
currents.
PHASE B HIGH SIDE SOURCE (PB_HS_S)
The source connection for the Phase B high side output
FET is the reference voltage for the gate drive on the high
side FET and also the low-voltage end of the bootstrap
capacitor.
PHASE B HIGH SIDE GATE (PB_HS_G)
This is the gate drive for the Phase B high side output FET.
This pin provides the gate bias to turn the external FET on or
source voltage. A low-impedance drive is used, ensuring
transient currents do not overcome an off-state driver and
allow pulses of current to flow in the external FETs. This
output has also been designed to resist the influence of
negative currents.
PHASE B BOOTSTRAP (PB_BOOT)
This is the bootstrap capacitor connection for phase B. A
capacitor connected between PC_HS_S and this pin
provides the gate voltage and current to drive the external
FET gate. Typically, the bootstrap capacitor selection is 10 to
20 times the gate capacitance. The voltage across this
capacitor is limited to about 15 V.
PHASE A LOW SIDE SOURCE (PA_LS_S)
The Phase A low side source is the pin used to return the
gate currents from the low side FET. Best performance is
realized by connecting this node directly to the source of the
low side FET for phase A.
PHASE A LOW SIDE GATE (PA_LS_G)
This is the gate drive for the Phase A low side output FET.
It provides high-current through a low-impedance to turn on
and off the low side FET. A low-impedance drive ensures
transient currents do not overcome an off-state driver and
allow pulses of current to flow in the external FET. This output
has also been designed to resist the influence of negative
currents.
PHASE A HIGH SIDE SOURCE (PA_HS_S)
The source connection for the Phase A high side output
FET is the reference voltage for the gate drive on the high
side FET and also the low-voltage end of the bootstrap
capacitor.
PHASE A HIGH SIDE GATE (PA_HS_G)
This is the gate drive for the Phase A high side output FET.
This pin provides the gate bias to turn the external FET on or
off. The gate voltage is limited to about 15 V above the FET
source voltage. A low-impedance drive is used, ensuring
transient currents do not overcome an off-state driver and
allow pulses of current to flow in the external FETs. This
output has also been designed to resist the influence of
negative currents.
PHASE A BOOTSTRAP (PA_BOOT)
This is the bootstrap capacitor connection for phase A. A
capacitor connected between PC_HS_S and this pin
provides the gate voltage and current to drive the external
FET gate. Typically, the bootstrap capacitor selection is 10 to
20 times the gate capacitance. The voltage across this
capacitor is limited to about 15 V.
off. The gate voltage is limited to about 15 V above the FET
33937A
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
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