参数资料
型号: MCZ33937EK
厂商: Freescale Semiconductor
文件页数: 34/48页
文件大小: 0K
描述: IC PRE-DRIVER 3PHASE 54-SOIC
标准包装: 26
系列: SMARTMOS™
配置: 3 相桥
输入类型: 非反相
延迟时间: 265ns
电流 - 峰: 600mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 15V
电源电压: 8 V ~ 40 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOICW-EP
包装: 管件
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEADTIME COMMAND
Deadtime prevents the turn-on of both transistors in the
same phase until the deadtime has expired. The deadtime
timer starts when a FET is commanded off (see Figure 6 and
Figure 13 ). The deadtime control is disabled by enabling the
FULLON mode.
The deadtime is set by sending the DEADTIME command
(100x xxx1), and then sending a calibration pulse of CS. This
pulse must be 16 times longer than the required deadtime
(see Figure 19 ). Deadtime is measured in cycle times of the
internal time base, f TB . This measurement is divided by 16
and stored in an internal register to provide the reference for
timing the deadtime between high and low gate transactions
in the same phase.
For example: the internal time base is running at 20 MHz
and a 1.5 μs deadtime is required. First a DEADTIME
command is sent (using the SPI), then a CS is sent. The CS
pulse is 16*1.5 = 24 μs wide. The IC measures this pulse as
24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in
Table 13. .DEADTIME Command
the deadtime register. Until the next deadtime calibration is
performed, 30 clock cycles will separate the turn off and turn
on gate signals in the same phase. The worst case error
immediately after calibration will be +0/-1 time base cycle, for
this example +0 ns/-50 ns. Note that if the internal time base
drifts, the effect on dead time will scale directly.
Sending a ZERO DEADTIME command (100x xxx0) sets
the deadtime timer to 0. However, simultaneous turn-on of
High Side and Low Side FETs in the same phase is still
prevented unless the FULLON command has been
transmitted. There is no calibration pulse expected after
receiving the ZERO DEADTIME command.
After RESET, deadtime is set to the maximum value of 255
time base cycles (typically 15 μs).
The IC ignores any SPI data that is sent during the
calibration pulse. If there are any transitions on SI or SCLK
while the Deadtime CS pulse is low, a Framing Error will be
generated, however, the CS pulse will be used to calibrate
the deadtime
SPI Data Bits
Write
7
1
6
0
5
0
4
x
3
x
2
x
1
x
0
ZERO/
CALIBRATE
Reset
x
x
x
x
CS
SCLK
SI
CS
SCLK
SI
Deadtime
DEADTIME
Command
Deadtime Calibration Pulse Pulse
SO
SO
Figure 19. Deadtime Calibration
33937A
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
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