参数资料
型号: MK10N512VMD100
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封装: 13 X 13 MM, MAPBGA-144
文件页数: 20/59页
文件大小: 1671K
代理商: MK10N512VMD100
Table 16. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
12
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
ns
EP9
EZP_CS negation to EZP_Q tri-state
12
ns
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.4.2 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 17. Flexbus switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Product Preview Data Sheet, Rev. 2, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
27
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