参数资料
型号: MK10N512VMD100
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封装: 13 X 13 MM, MAPBGA-144
文件页数: 38/59页
文件大小: 1671K
代理商: MK10N512VMD100
6.8.1 CAN
6.8.2 DSPI Switching Specifications for Low-speed Operation
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 28. Master Mode DSPI Timing (Low-speed mode)
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.71
3.6
V
Frequency of operation
12.5
MHz
DS1
DSPI_SCK output cycle time
4 x tBCLK
ns
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) - 4
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) - 4
ns
DS5
DSPI_SCK to DSPI_SOUT valid
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
DS3
DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data
Data
Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 19. DSPI Classic SPI Timing — Master Mode
Peripheral operating requirements and behaviors
K10 Sub-Family Product Preview Data Sheet, Rev. 2, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
43
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