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参数资料
| 型号： | MM908E626AVEK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 32 MHz, MICROCONTROLLER, PDSO54 |
| 封装： | 5.10 X 10.30 MM, 0.65 MM PITCH, LEAD FREE, SOIC-54 |
| 文件页数： | 22/43页 |
| 文件大小： | 842K |
| 代理商： | MM908E626AVEK |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
29
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CSA—H-bridges Current Sense Amplification Select Bit
This read/write bit selects the current sense amplification
of the H-bridges. Reset clears the CSA bit.
1 = Current sense amplification set for measuring 0.5 A.
0 = Current sense amplification set for measuring 2.5 A.
CLS2:CLS0—H-Bridge Current Limitation Selection Bits
These read/write bits select the current limitation value
according to Table . Reset clears the CLS2:CLS0 bits.
Switchable VDD Outputs
The HVDD pin is a switchable VDD output pin. It can be
used for driving external circuitry that requires a VDD voltage.
The output is enabled with bit PSON in the System Control
Register and can be switched on/off with bit HVDDON in the
Power Output Register. Low or high voltage conditions (LVI/
HVI) have no influence on this circuitry.
HVDD Over-temperature Protection
Over-temperature protection is enabled if the high
temperature reset is enabled.
HVDD Over-current Protection
The HVDD output is protected against over-current. In the
event the over-current limit is or was reached, the output
automatically switches off and the HVDD over-current flag in
the System Status Register is set.
System Control Register (SYSCTL)
PSON—Power Stages On Bit
This read/write bit enables the power stages (half-bridges,
LIN transmitter and HVDD output). Reset clears the PSON
bit.
1 = Power stages enabled.
0 = Power stages disabled.
SRS0:SRS1—LIN Slew Rate Selection Bits
These read/write bits enable the user to select the
appropriate LIN slew rate for different baud rate
configurations as shown in Table .
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
Go to STOP Mode Bit (GS)
This write-only bit instructs the 908E626 to power down
and go into STOP mode. Reset or CPU interrupt requests
clear the GS bit.
1 = Power down and go into STOP mode
0 = Not in STOP mode
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation
in the transmitter, software is advised to turn the transmitter
off immediately.
1 = Transmitter operating in current limitation region.
0 = Transmitter not operating in current limitation
region.
HVDD_OCF—HVDD Output Over-current Flag Bit
This read/write flag is set on an over-current condition at
the HVDD pin. Clear HVDD_OCF and enable the output by
writing a logic [1] to the HVDD_OCF Flag. Reset clears the
Table 8. H-Bridge Current Limitation Value Selection
Bits
CLS2
CLS1
CLS0
Current Limit
000
No Limit
001
010
011
55 mA (typ)
100
260 mA (typ)
101
370 mA (typ)
110
550 mA (typ)
111
740 mA (typ)
Register Name and Address: SYSCTL - $03
Bit7
6
5
4
3
2
1
Bit0
Read
PSON
SRS1
SRS0
0
Write
GS
Reset
0
0000
0
Table 9. LIN Slew Rate Selection Bits
SRS1
SRS0
LIN Slew Rate
0
Initial Slew Rate (20 kBaud)
0
1
Slow Slew Rate (10 kBaud)
1
0
High Speed II (8x)
1
High Speed I (4x)
Register Name and Address: SYSSTAT - $0c
Bit7
6
5
4
3
2
1
Bit0
Read
0
LINCL HVDD
_OCF
0
LVF
HVF
HB_
OCF
HTF
Write
Reset
0000
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相关代理商/技术参数 |
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|---|---|
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