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参数资料
| 型号： | MM908E626AVEK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 32 MHz, MICROCONTROLLER, PDSO54 |
| 封装： | 5.10 X 10.30 MM, 0.65 MM PITCH, LEAD FREE, SOIC-54 |
| 文件页数： | 24/43页 |
| 文件大小： | 842K |
| 代理商： | MM908E626AVEK |
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Analog Integrated Circuit Device Data
30
Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no
effect.
1 = Over-current condition on HVDD has occurred.
0 = No over-current condition on HVDD has occurred.
LVF—Low Voltage Bit
This read only bit is a copy of the LVF bit in the Interrupt
Flag Register.
1 = Low voltage condition has occurred.
0 = No low voltage condition has occurred.
HVF—High Voltage Sensor Bit
This read-only bit is a copy of the HVF bit in the Interrupt
Flag Register.
1 = High voltage condition has occurred.
0 = No high voltage condition has occurred.
HB_OCF—H-Bridge Over-current Flag Bit
This read / write flag is set on an over-current condition at
the H-Bridges. Clear HB_OCF and enable the H-Bridge
driver by writing a logic [1] to HB_OCF. Reset clears the
HB_OCF bit. Writing a logic [0] to HB_OCF has no effect.
1 = Over-current condition on H-Bridges has occurred.
0 = No over-current condition on H-Bridges has
occurred.
HTF—Over-temperature Status Bit
This read-only bit is a copy of the HTF bit in the Interrupt
Flag Register.
1 = Over-temperature condition has occurred.
0 = No over-temperature condition has occurred.
AUTONOMOUS WATCHDOG (AWD)
The Autonomous Watchdog module consists of three
functions:
Watchdog function for the CPU in RUN mode
Periodic interrupt function in STOP mode
The Autonomous Watchdog module allows to protect the
CPU against code runaways.
The AWD is enabled if AWDIE, AWDRE in the AWDCTL
Register is set. If this bit is cleared, the AWD oscillator is
disabled and the watchdog switched off.
Watchdog
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode
is activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
Periodic interrupt is only available in STOP mode. It is
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
Autonomous Watchdog Control Register (AWDCTL)
AWDRST—Autonomous Watchdog Reset Bit
This write-only bit resets the Autonomous Watchdog
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
1 = Reset AWD and restart timeout period.
0 = No effect.
AWDRE—Autonomous Watchdog Reset Enable Bit
This read/write bit enables resets on AWD timeouts. A
reset on the RST_A is asserted when the Autonomous
Watchdog has reached the timeout and the Autonomous
Watchdog is enabled. AWDRE is one-time setable (write
once) after each reset. Reset clears the AWDRE bit.
1 = Autonomous watchdog enabled.
0 = Autonomous watchdog disabled.
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
This read/write bit enables CPU interrupts by the
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
1 = CPU interrupt requests from AWDF enabled
0 = CPU interrupt requests from AWDF disabled
AWDR—Autonomous Watchdog Rate Bit
This read/write bit selects the clock rate of the
Autonomous Watchdog. Reset clears the AWDR bit.
1 = Fast rate selected (10 ms).
0 = Slow rate selected (20 ms).
Register Name and Address: AWDCTL - $0a
Bit7
6
5
4
3
2
1
Bit0
Read
00
0
AWDRE
AWDIE
0
AWDR
Write
AWDRST
Reset
00
0
Notes
18.
This bit must always be set to 0.
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