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参数资料
| 型号： | MMDF3N04HDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH DUAL 3.4A 40V 8SOIC |
| 产品变化通告： | Product Obsolescence 14/Apr/2010 |
| 产品目录绘图： | MOSFET 8-SOIC |
| 标准包装： | 10 |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 40V |
| 电流 - 连续漏极(Id) @ 25° C： | 3.4A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 80 毫欧 @ 3.4A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 28nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 900pF @ 32V |
| 功率 - 最大： | 1.39W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 其它名称： | MMDF3N04HDR2GOSDKR |
MMDF3N04HD
di/dt = 300 A/ m s
Standard Cell Density
t rr
High Cell Density
t a
t rr
t b
t, TIME
Figure 11. Reverse Recovery Time (t rr )
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain ? to ? source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T C ) of 25 ° C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance ?
General Data and Its Use.”
Switching between the off ? state and the on ? state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the
transition time (t r , t f ) does not exceed 10 m s. In addition the
total power averaged over a complete switching cycle must
not exceed (T J(MAX) ? T C )/(R q JC ).
A power MOSFET designated E ? FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non ? linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E ? FETs can withstand the stress of
drain ? to ? source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (I D ), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I D can safely be
assumed to equal the values indicated.
100
10
V GS = 20 V
SINGLE PULSE
T C = 25 ° C
1 ms
160
120
I D = 9 A
10 ms
1
0.1
dc
R DS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
80
40
0.01
0.1
1
10
100
0
25
50
75
100
125
150
V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
T J , STARTING JUNCTION TEMPERATURE ( ° C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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