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参数资料
| 型号： | MMSF2P02ER2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 小信号晶体管 |
| 英文描述： | 2500 mA, 20 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封装： | MINIATURE, CASE 751-07, SOP-8 |
| 文件页数： | 4/9页 |
| 文件大小： | 247K |
| 代理商： | MMSF2P02ER2 |
MMSF2P02E
http://onsemi.com
4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
C,
CAP
ACIT
ANCE
(pF)
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
V
GS
,GA
TET
OSOURCE
VOL
TAGE
(VOL
TS)
Qg, TOTAL GATE CHARGE (nC)
Figure 8. GatetoSource and
DraintoSource Voltage versus Total Charge
02
4
6
8
ID = 2 A
TJ = 25°C
VGS
6
3
0
12
9
16
12
8
4
0
VDS
QT
Q1
Q2
Q3
10
12
10
0
10
15
25
VGS
VDS
TJ = 25°C
VDS = 0 V
VGS = 0 V
1000
800
600
400
200
0
20
Ciss
Coss
Crss
55
Ciss
Crss
30
V
DS
,DRAINT
OSOURCE
VOL
TAGE
(VOL
TS)
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相关代理商/技术参数 |
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