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参数资料
| 型号： | MPC740ARX266TX |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 4/44页 |
| 文件大小： | 280K |
| 代理商： | MPC740ARX266TX |
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12
MPC750A RISC Microprocessor Hardware Specications
Electrical and Thermal Characteristics
1.4.2.2 60x Bus Input AC Specications
Table 9 provides the 60x bus input AC timing specications for the MPC750 as dened in Figure 4 and
Figure 5. Input timing specications for the L2 bus are provided in Section 1.4.2.5, “L2 Bus Input AC
Specications.
Table 9. 60x Bus Input AC Timing Specifications1
At recommended operating conditions (See Table 3)
Num
Characteristic
200, 233, 266 MHz
Unit
Notes
Min
Max
10a
Address/Data/Transfer Attribute Inputs Valid
to SYSCLK (Input Setup)
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input
Setup)
3.0
—
ns
3
10c
Mode select input setup to HRESET
(DRTRY, TLBISYNC)
8—
t
sysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute
Inputs Invalid (Input Hold)
0
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input
Hold)
0
—
ns
3
11c
HRESET to mode select input hold (DRTRY,
TLBISYNC)
0
—
ns
4,6,7
Notes:
1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/Data/Transfer Attribute inputs are composed of the following—A[0–31], AP[0–3], TT[0–4], TBST,
TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other signal inputs are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
6. Guaranteed by design and characterization.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
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