参数资料
型号: MPC745BPX350LE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 350 MHz, RISC PROCESSOR, PBGA255
封装: 21 X 21 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-255
文件页数: 39/60页
文件大小: 1559K
代理商: MPC745BPX350LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 7.0
44
Freescale Semiconductor
System Design Information
Figure 24. JTAG Interface Connection
HRESET
HRESET 6
From Target
Board Sources
HRESET
13
SRESET
NC
11
VDD_SENSE
6
5 1
15
2 k
10 k
10 k
10 k
OVDD
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP
Header
14 2
Key
QACK
OVDD
10 k
OVDD
10 k
OVDD
10 k
10 k
QACK
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 k
4
OVDD
1
2 k
3
0
5
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC755. Connect
pin 5 of the COP header to OVDD with a 10-k pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the
processor in order to fully control the processor as shown above.
TRST 6
10 k
OVDD
相关PDF资料
PDF描述
MPC755BPX350LE 32-BIT, 350 MHz, RISC PROCESSOR, PBGA360
MPC755CPX400LE 32-BIT, 400 MHz, RISC PROCESSOR, PBGA360
MPC745BVT300LE 32-BIT, 300 MHz, RISC PROCESSOR, PBGA255
MPC755BVT300LE 32-BIT, 300 MHz, RISC PROCESSOR, PBGA360
MPC823ZC25 32-BIT, RISC PROCESSOR, PBGA256
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