参数资料
型号: MPC8240LZU200X
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件页数: 26/58页
文件大小: 596K
代理商: MPC8240LZU200X
32
MPC8240 Integrated Processor Hardware Specications
PLL Conguration
Notes:
1
Place pull-up resistors of 120 Ohms or less on the TEST[0:1] pins.
2
Treat these pins as no connects unless using debug address functionality.
3
This pin has an internal pull-up resistor which is enabled only when the MPC8240 is in the reset state.
The value of the internal pull-up resistor is not guaranteed, but is sufcient to insure that a '1' is read into
conguration bits during reset.
4
This pin is a reset conguration pin.
5
DL[0] is a reset conguration pin and has an internal pull-up resistor which is enabled only when the
MPC8240 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufcient
to insure that a ‘1' is read into conguration bits during reset.
6
Multi-pin signals such as AD[0:31] or DL[0:31] have their physical package pin numbers listed in order
corresponding to the signal names. Ex: AD0 is on pin C22, AD1 is on pin D22,... AD31 is on pin V25.
7
GNT4 is a reset conguration pin and has an internal pull-up resistor which is enabled only when the
MPC8240 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufcient
to insure that a '1' is read into conguration bits during reset.
8
Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this PCI control pin to LVdd.
9VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to OVdd.
11 Recommend a weak pull-up resistor (2K – 10K Ohm) be placed on this pin to GVdd.
12 This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is
sufcient to prevent unused inputs from oating.
13 Output Valid specications for this pin are memory interface mode dependent (Registered or
Flow-through), see Table 9.
14 Non-DRAM Access Output Valid specication applies to this pin during non-DRAM accesses, see speci-
cation 12b3 in Table 9.
15 This pin is affected by programmable PCI_HOLD_DEL parameter, see Section 1.4.2.4.1, “PCI Signal
16 This pin is an open drain signal.
17 This pin can be programmed to be driven (default) or can be programmed to be open drain; see PMCR2
register description in the MPC8240 User’s Manual for details.
18 This pin is a Sustained Tri-State pin as dened by the PCI Local Bus Specication.
19 Max input voltage tolerance is LVdd based. See Table 2. for details.
1.6 PLL Conguration
The MPC8240’s internal PLLs are congured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL conguration signals set both the Peripheral Logic/Memory Bus PLL (VCO)
frequency of operation for the PCI-to-Memory frequency multiplying and the 603e CPU PLL (VCO)
frequency of operation for Memory-to-CPU frequency multiplying. The PLL congurations for the
MPC8240 is shown in Table 18.
Manufacturing Pins
DA2
C25
Output
OVdd
DRV_PCI
2
DA[11:13]
AD26 AF17 AF19
Output
OVdd
DRV_PCI
2,6
DA[14:15]
F1 J2
Output
GVdd
DRV_MEM_ADDR
2,6
Table 17. MPC8240 Pinout Listing (Continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output Driver
Type
Notes
相关PDF资料
PDF描述
MPC8240LZU250X 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352
MPC8240RZU266X 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU300X 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU350X 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
MPC8270CVVQLDA 32-BIT, 333 MHz, RISC PROCESSOR, PBGA480
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